(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of integrating salicide and borderless contact processes in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, logic products are often produced using salicide (self-aligned silicide) processes in order to obtain higher circuit performance. In silicidation, a refractory metal layer is deposited and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the gate electrode and source and drain regions. The silicided gate and source/drain regions have lower resistance than non-silicided regions, especially in smaller geometries, and hence, higher circuit performance.
In order to shrink cell size, a borderless contact is one of the most important processes in the art. Of major concern is the borderless contact leakage current for shallow junctions, especially at the edge of the shallow trench isolation (STI) regions. It is desired to find a method of integrating the salicide and the borderless contact processes while avoiding the leakage current problem at the STI edge.
U.S. Pat. No. 5,545,581 to Armacost et al teaches depositing a nitride layer over salicide to be used as an etch stop when making a contact. U.S. Pat. No. 5,937,325 to Ishida forms a salicide using two RTA steps, first forming the salicide over a gate, then forming a salicide over the source/drain. U.S. Pat. Nos. 5,719,079 to Yoo et al. and 5,674,781 to Huang et al. teach borderless contact processes but without etch stop layers. U.S. Pat. No. 5,516,726 to Kim et al. discloses an etch stop for a borderless contact process, but no salicide process.